DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 98

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–4
Figure 2–1. Byte Enable Functional Waveform
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
don't care: q (asynch)
contents at a3
contents at a4
contents at a0
contents at a1
contents at a2
1
address
byteena
inclock
wren
data
Table 2–4
Table 2–4. byteena Controls in x20 Data Width
If you use the ECC feature on the M20K blocks, you cannot use the byte enable
feature.
Figure 2–1
RAM blocks. When a byte-enable bit is deasserted during a write cycle, the
corresponding data byte output can appear as either a “don’t care” value or the
current data at that location. The output value for the masked byte is controllable with
the Quartus II software. When a byte-enable bit is asserted during a write cycle, the
corresponding data byte output also depends on the setting chosen in the Quartus II
software.
XXXXXXXX
FFFFFFFF
XXXX
an
FFFFFFFF
byteena[1:0]
11(default)
lists the byteena controls in the x20 data width.
shows how the wren and byteena signals control the operations of the
doutn
10
01
FFFFFFFF
1000
a0
FFFFFFFF
ABXXXXXX
FFFFFFFF
0100
a1
XXCDXXXX
ABCDEF12
0010
a2
[19:10]
[19:10]
XXXXEFXX
—
ABFFFFFF
0001
a3
FFCDFFFF
Data Bits Written
XXXXXX12
Chapter 2: Memory Blocks in Stratix V Devices
FFFFEFFF
1111
a4
ABCDEF12
FFFFFF12
May 2011 Altera Corporation
XXXX
a0
XXXXXXXX
ABCDEF12
[9:0]
[9:0]
ABFFFFFF
—
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