DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 437

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
Figure 2–16. Six Channels Configured in Bonded Configuration Using ATX PLL
Note to
(1) Serial clock from the ×1 clock lines.
May 2011 Altera Corporation
Figure
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
Parallel Clock
Serial Clock
Parallel and Serial Clocks
2–16:
(1)
(1)
(1)
(1)
(1)
Local Clock Divider
Central Clock Divider
Local Clock Divider
Local Clock Divider
Central Clock Divider
Local Clock Divider
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Deserializer
Deserializer
Deserializer
Deserializer
Deserializer
Deserializer
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
Reference
Reference
Reference
Reference
Reference
Reference
CDR
CDR
CDR
CDR
CDR
CDR
Clock
Clock
Clock
Clock
Clock
Clock
Input
Input
Input
Input
Input
Input
Stratix V Device Handbook Volume 3: Transceivers
×6 Clock Lines
×1 Clock Lines
ATX PLL
ATX PLL
2–21