DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 343

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 10: SEU Mitigation in Stratix V Devices
Error Detection Pin Description
Table 10–4. Fault Injection Register
Error Detection Pin Description
Table 10–5. CRC_ERROR Pin Description
May 2011 Altera Corporation
Description
Content
CRC_ERROR
Pin Name
Others
Bit[46] Bit[45] Bit[44] Bit[43]
0
0
0
I/O, output, or
output
open-drain
Pin Type
Table 10–4
injection.
Table 10–5
Error Type
0
0
0
Active high signal indicating that the error detection circuit has detected errors in the
configuration CRAM bits. This is an optional pin and is used when you enable the error
detection CRC circuit. When you disable the error detection CRC circuit, it is an user I/O
pin. When using the WYSIWYG function, you can route the crcerror port from the
WYSIWYG atom to the dedicated CRC_ERROR pin or any user I/O. To route the crcerror
port to user I/O, you must insert a D-type flipflop in between the crcerror port and the
I/O.
By default, the Quartus II software sets the CRC_ERROR pin as output open-drain when
you enable the error detection CRC circuitry. By option, you can set this pin to be an
output by turning off the Enable open-drain on CRC_ERROR pin option on the Error
Detection CRC page of the Device and Pin Option dialog box in the Quartus II software.
If the CRC_ERROR pin is used as an output, you must ensure that the V
which the pin resides meet the input voltage specification of the system receiving the
signal. Using the pin as an open-drain provides an advantage on the voltage leveling. To
use the CRC_ERROR pin as an open-drain, you can tie this pin to V
resistor. Alternatively, depending on the input voltage specification of the system
receiving the signal, tie this pin to a different pull-up voltage.
0
0
1
lists how the fault injection register is implemented and describes error
lists the CRC_ERROR pin.
Bit[46..43]
0
1
0
No error injection
Single error injection
Double-adjacent error
injection
Reserved
Error Injection Type
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Description
Depicts the location
of the injected error
in the first data
frame.
the Injected Error
Byte Location of
Bit[42..32]
CCPGM
Depicts the location
of the bit error and
corresponds to the
error injection type
selection.
Error Byte Value
CCIO
through a 10-k
Bit[31..0]
of the bank in
10–5