DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 146

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–6
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Clock Sources Per Quadrant
1
There are 33 section clock (SCLK) networks available in each spine clock that can
drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and
two core reference clocks. The SCLKs are the clock resources to the core functional
blocks, PLLs, and I/O interfaces of the device.
GCLK, RCLK, PCLK, or the PLL feedback clock networks in each spine clock.
A spine clock is another layer of routing between the GCLKs, RCLKs, and PCLK
networks before each clock is connected to the clock routing for each LAB row. The
settings for spine clocks are transparent. The Quartus II software automatically routes
the spine clock based on the GCLK, RCLK, and PCLK networks.
Figure 4–7. Hierarchical Clock Networks Per Spine Clock
Notes to
(1) The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing to the SCLKs. The total number of clock
(2) There are up to 83 PCLKs that can drive the SCLKs in each spine clock in the largest device.
(3) There are up to 23 RCLKs that can drive the SCLKs in each spine clock in the largest device.
(4) The PLL feedback clock is the clock from the PLL that drives into the SCLKs.
(5) The column I/O clock is the clock that drives the column I/O core registers and I/O interfaces.
(6) The core reference clock is the clock that feeds into the PLL as the PLL reference clock.
(7) The row clock is the clock source to the LAB, memory blocks, and row I/O interfaces in the core row.
PLL feedback clock
resources must not exceed the SCLK limits in each region to ensure successful design fitting in the Quartus II
software.
Figure
4–7:
GCLK
RCLK
PCLK
(4)
16
83 (2)
23 (3)
5
SCLK
Chapter 4: Clock Networks and PLLs in Stratix V Devices
33
Figure 4–7
(Note 1)
shows SCLKs driven by the
Clock Networks in Stratix V Devices
9
2
6
May 2011 Altera Corporation
Column I/O clock
Core reference clock
Row clock
(7)
(5)
(6)