DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 435

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
May 2011 Altera Corporation
Figure 2–15. Five Channels Configured in Bonded Configuration
Notes to
(1) Serial clock from the ×1 clock lines.
(2) For channel 4, you cannot use the CDR for the receiver because the channel PLL is being used as a CMU PLL.
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Figure
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
CMU PLL
Parallel Clock
Serial Clock
Parallel and Serial Clocks
2–15:
(1)
(1)
(1)
(1)
(1)
(1)
Local Clock Divider
Central Clock Divider
Local Clock Divider
Local Clock Divider
Central Clock Divider
Local Clock Divider
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Receiver PCS
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Clock Divider
Deserializer
Deserializer
Deserializer
Deserializer
Deserializer
Deserializer
Stratix V Device Handbook Volume 3: Transceivers
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
Receiver PMA
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
To Transmitter Channel
Reference
Reference
Reference
Reference
Reference
Reference
CDR
CDR
CDR
CDR
CDR
CDR
(2)
Clock
Clock
Clock
Clock
Clock
Clock
Input
Input
Input
Input
Input
Input
×6 Clock Lines
×1 Clock Lines
2–19