DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 267

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Figure 7–13. IOE Output and Output-Enable Path Registers for Stratix V Devices
Notes to
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
(3) The half-rate clock comes from the PLL while the alignment clock comes from the write-leveling delay chains.
(4) These registers are used in DDR3 SDRAM interfaces for write-leveling purposes.
(5) The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset
Half-Rate Clock (3)
From Core (2)
From Core (2)
(wdata2) (2)
(wdata0) (2)
(wdata3) (2)
(wdata1) (2)
From Core
From Core
From Core
From Core
between them.
Figure
Half Data Rate to Single Data Rate Output-Enable Registers
7–13:
D
D
D
D
D
D
DFF
DFF
Half Data Rate to Single Data Rate Output Registers
DFF
DFF
DFF
DFF
Q
Q
Q
Q
Q
Q
Alignment
Clock (3)
0
1
0
1
0
1
Clock Alignment Clock (3)
Clock Alignment Clock (3)
clk (3)
D
D
D
DFF
DFF
DFF
Q
Q
Q
D
D
D
DFF
DFF
DFF
Q
Q
Q
<add_output_cycle_delay>
<add_output_cycle_delay>
<add_output_cycle_delay>
D
D
D
DFF
DFF
DFF
Q
Q
Q
(Note 1)
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
enaoutputcycledelay[2..0]
enaoutputcycledelay[2..0]
enaoutputcycledelay[2..0]
Clock (5)
Write
D
D
D
DFF
DFF
DFF
enaphasetransferreg
enaphasetransferreg
enaphasetransferreg
Alignment Registers (4)
Alignment Registers (4)
Q
Q
Q
0
1
0
1
0
1
dataout
dataout
dataout
DFF
DFF
Double Data Rate Output-Enable Registers
OE Reg A
DFF
OE Reg B
Output Reg Ao
Output Reg Bo
DFF
D
D
D
D
Double Data Rate Output Registers
Q
Q
Q
Q
OE
OE
1
0
1
0
OR2
TRI
DQ or DQS