DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 410

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–38
Stratix V Device Handbook Volume 3: Transceivers
Transmitter 10G PCS Datapath
Clock Compensation Mode
The receiver FIFO is configured in clock compensation mode for the 10GBASE-R
configuration. In this mode, the FIFO deletes idles OR ordered sets and inserts only
idles to compensate up to a ±100 PPM clock difference between the remote
transmitter and the local receiver.
Generic Mode
The receiver FIFO is configured in generic mode for the Interlaken configuration. In
this mode, the receiver FIFO provides the FIFO partially empty and FIFO full status
signals to the FPGA fabric to control the read side of the FIFO.
Phase Compensation Mode
The receiver FIFO is configured in phase compensation mode for the 10G custom
configuration. In this mode, the FIFO compensates for the phase difference between
the FIFO write clock and the read clock.
The transmitter channel datapath shown in
following blocks:
■
■
■
■
■
■
■
Transmitter FIFO
The transmitter FIFO provides an interface between the transmitter channel PCS and
the FPGA fabric.
In a 10GBASE-R configuration, the transmitter FIFO receives data from the FPGA
fabric. The data output from this block goes to the 64B/66B encoder.
In an Interlaken configuration, the transmitter FIFO sends a control signal to indicate
whether it is ready to receive data from the FPGA fabric. The user logic sends the data
to the FIFO only if this signal is asserted. Data output from the transmitter FIFO block
goes to the frame generator in this configuration.
Frame Generator
The frame generator block
protocol. This block takes the data from the transmitter FIFO and encapsulates the
payload and the burst/idle control words from the FPGA fabric with the framing
layer’s control words, such as the synchronization word, scrambler state word, skip
word, and diagnostic word, to form a metaframe. The Interlaken PHY IP MegaWizard
Plug-In Manager interface provides an option to set the metaframe length.
“Transmitter FIFO”
“Frame Generator” on page 1–38
“CRC-32 Generator” on page 1–39
“64B/66B Encoder” on page 1–40
“Scrambler” on page 1–40
“Disparity Generator” on page 1–41
“Transmitter Gear Box” on page 1–41
(Figure
1–35) is designed to support the Interlaken
Chapter 1: Transceiver Architecture in Stratix V Devices
Figure 1–29 on page 1–33
May 2011 Altera Corporation
consists of the
10G PCS Architecture