DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 121

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
Variable Precision DSP Block Resource Descriptions
May 2011 Altera Corporation
Input Registers Bank
The positive edge of the clock signal triggers all variable precision DSP block registers
and clears them after power up. Each multiplier operand can feed an input register or
a multiplier directly, bypassing the input registers. The following variable precision
DSP block signals control the input registers within the variable precision DSP block:
■
■
■
Besides the registers for the data and dynamic control signals, there are also two sets
of delay registers in the input register bank. The delay registers are used to balance the
latency requirements when both the input cascade and chainout features are used.
This is only supported in 18 x 18 mode.
CLK[2..0]
ENA[2..0]
ACLR[0]
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
3–5