DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 101

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Overview
Figure 2–5. Output Latch Clear in Stratix V Devices
May 2011 Altera Corporation
Asynchronous Clear
Error Correction Code Support
rden
aclr
clr at
latch
out
clk
M20K memory blocks support asynchronous clear on output latches and output
registers. Therefore, if your RAM does not use output registers, clear the RAM
outputs using the output latch asynchronous clear. Because the clear is an
asynchronous signal, it is generated at any time. The internal logic extends the clear
pulse until the next rising edge of the output clock. When the clear is asserted, the
outputs are cleared and stay cleared until the next read cycle.
Figure 2–5
M20K blocks have built-in support for ECC when in x32-wide simple dual-port mode.
ECC allows you to detect and correct data errors at the output of the memory. ECC
can perform single-error correction, double-adjacent-error correction, and
triple-adjacent-error detection in a 32-bit word; however, ECC cannot detect four or
more errors.
The M20K runs slower than non-ECC simple-dual port mode when ECC is engaged;
however, you can enable optional ECC pipeline registers before the output decoder to
achieve the same performance as non-ECC simple-dual port mode at the expense of
one cycle of latency.
The M20K ECC status is communicated with two ECC status flag signals—e (error)
and ue (uncorrectable error). The status flags are part of the regular output from the
memory block. When ECC is engaged, you cannot access two of the parity bits
because they are replaced by the ECC status flag.
D 0
shows the output latch clear in Stratix V devices.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
D 1
D 2
2–7