DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 389

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
PMA Architecture
Table 1–3. Transmission Bit Order for the Bit Reversal Feature for Stratix V Devices
May 2011 Altera Corporation
Not enabled (default)
Enabled
Transmitter Bit Reversal
Feature
Calibration Blocks
f
c
Transmitter Bit Reversal
Table 1–3
enabled.
If reversal is asserted midway through a serializer word, the word will be corrupted.
Transmitter Protocol Specific
There are two PCIe features in the transmitter PMA section—receiver detect and
electrical idle.
PCIe Receiver Detect
The transmitter buffers have a built-in receiver detection circuit for use in the PCIe
configuration for Gen1 and Gen2 data rates. This circuit detects if there is a receiver
downstream by sending out a pulse on the common mode of the transmitter and
monitoring the reflection.
PCIe Electrical Idle
The transmitter output buffers support transmission of PCIe electrical idle (or
individual transmitter tri-state).
For more information about receiver detect and electrical idle, refer to the PCI Express
PHY IP Core chapter in the
Stratix V GX and GS devices contain calibration circuits that calibrate the OCT
resistors and the analog portions of the transceiver blocks to ensure that the
functionality is independent of PVT variations.
The calibration block internally generates a constant internal reference voltage,
independent of PVT variations. It uses the internal reference voltage and external
reference resistor (you must connect the resistor to the RREF pin) to generate constant
reference currents. These reference currents are used by the analog block calibration
circuit to calibrate the transceiver blocks.
You must connect a separate 2 k (tolerance max ±1%) external resistor on each RREF
pin to ground. To ensure the calibration block operates properly, the RREF resistor
connection in the board must be free from external noise.
LSB to MSB
MSB to LSB
For example:
■
■
8-bit—D[7:0]rewired to D[0:7]
10-bit—D[9:0]rewired to D[0:9]
lists the transmission bit order with and without the transmitter bit reversal
Single-Width Mode
(8 or 10 Bit)
Altera Transceiver PHY IP Core User
LSB to MSB
MSB to LSB
For example:
■
■
16-bit—D[15:0]rewired to D[0:15]
20-bit—D[19:0]rewired to D[0:19]
Stratix V Device Handbook Volume 3: Transceivers
Double-Width Mode
(16 or 20 Bit)
Guide.
1–17