DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 190

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–14
Table 5–10. Stratix V MultiVolt I/O Support
OCT Support and I/O Termination Schemes
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Notes to
(1) The pin current may be slightly higher than the default value. You must verify that the driving device’s V
(2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3.0 V or 3.3 V.
(3) Each I/O bank of a Stratix V device has its own VCCIO pins and supports only one V
do not violate the applicable Stratix V V
standard is not supported when V
LVDS output operations are only supported when V
V
CCIO
1.25
1.35
1.2
1.5
1.8
2.5
3.0
Table
(3)
MultiVolt I/O Interface
(V)
5–10:
1.2
v
—
—
—
—
—
—
The Stratix V architecture supports the MultiVolt I/O interface feature that allows
Stratix V devices in all packages to interface with systems of different supply voltages.
You can connect the VCCIO pins to a 1.2-, 1.25-, 1.35-, 1.5-, 1.8-, 2.5-, or 3.0-V power
supply, depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when VCCIO pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems.)
The Stratix V VCCPD power pins must be connected to a 2.5- or 3.0-V power supply.
Using these power pins to supply the pre-driver power to the output buffers increases
the performance of the output pins.
Stratix V devices feature dynamic R
matching and termination capabilities. OCT maintains signal quality, saves board
space, and reduces external component costs.
Stratix V devices support the following OCT schemes:
■
■
■
■
■
R
R
Dynamic R
Dynamic R
R
1.25 1.35
—
v
—
—
—
—
—
S
T
D
with and without calibration
with calibration
for differential LVDS I/O standards
CCIO
—
—
v
—
—
—
—
is 3.0 V. The LVDS input operations are supported when V
IL
Input Signal (V)
maximum and V
T
S
1.5
for single-ended I/O standards
—
—
—
v
v
—
—
for single-ended I/O standards
(Note 1)
CCIO
1.8
—
—
—
v
v
—
—
is 2.5 V.
IH
2.5
—
—
—
—
—
v
v
minimum voltage specifications.
3.0
(2)
(2)
—
—
—
—
—
v
v
S
Table 5–10
and R
3.3
(2)
(2)
—
—
—
—
—
v
v
1.2
v
CCIO
T
—
—
—
—
—
—
OCT to provide I/O impedance
, either 1.2, 1.25, 1.35, 1.5, 1.8, or 3.0 V. The LVDS I/O
lists Stratix V MultiVolt I/O support.
1.25 1.35
—
v
—
—
—
—
—
CCIO
Chapter 5: I/O Features in Stratix V Devices
OCT Support and I/O Termination Schemes
v
—
—
—
—
—
—
OL
is 1.2, 1.25, 1.35, 1.5, 1.8, or 2.5 V. The
Output Signal (V)
maximum and V
1.5
—
—
—
v
—
—
—
May 2011 Altera Corporation
1.8
—
—
—
—
v
—
—
OH
2.5
—
—
—
—
—
v
—
minimum voltages
3.0
—
—
—
—
—
—
v
3.3
v
—
—
—
—
—
—