DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 265

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
May 2011 Altera Corporation
Dynamic On-Chip Termination Control
f
1
Figure 7–10
Figure 7–10. Write-Leveling Delay Chains and Multiplexers for Stratix V Devices
Note to
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have
The –90° write clock of the UniPHY megafunction feeds the write-leveling circuitry to
produce the clock to generate the DQS and DQ signals. During initialization, the
UniPHY megafunction picks the correct write-leveled clock for the DQS and DQ
clocks for each DQ/DQS group after sweeping all the available clocks in the write
calibration process. The DQ clock output is –90° phase-shifted compared to the DQS
clock output.
The UniPHY megafunction dynamically calibrates the alignment for read and write
leveling during the initialization process.
For more information about the UniPHY megafunction, refer to
Volume 3: Implementing Altera Memory Interface IP
Handbook.
Figure 7–11
Figure 7–11. Dynamic OCT Control Block for Stratix V Devices
Note to
(1) The write clock comes from either the PLL or the write-leveling delay chain.
The block includes all the registers required to dynamically turn on-chip parallel
termination (R
one memory interface in each I/O sub-bank when you use the leveling delay chain.
Figure
Figure
7–10:
7–11:
shows the dynamic OCT control block.
shows the Stratix V write-leveling circuitry.
Write clk
T
OCT) on during a read and turn R
(-90
0
)
OCT Half-Rate Clock
OCT Control Path
OCT Control
2
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
HDR Block
DFF
Write Clock (1)
Resynchronization
Registers
of the External Memory Interface
DFF
T
Write-Leveled DQ Clock
Write-Leveled DQS Clock
OCT off during a write.
OCT Enable
(Note 1)
7–21