DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 141

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV51005-1.2
Clock Networks in Stratix V Devices
Table 4–1. Clock Resources in Stratix V Devices—Preliminary
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51005-1.2
Clock input pins
GCLK networks
RCLK networks
PCLK networks
GCLKs and RCLKs
per quadrant
GCLKs and RCLKs
per device
Notes to
(1) This applies to all Stratix V devices except 5SGSD6, 5SGSD8 devices.
(2) This only applies to 5SGSD6 and 5SGSD8 devices.
(3) There are 228 PCLKs in 5SGXA3 and 5SGXA4 devices, 282 PCLKs in 5SGXB5 and 5SGXB6 devices, 306 PCLKs in 5SGXA5 and 5SGXA7
Clock Resource
devices, and 309 PCLKs in 5SGSD6 and 5SGSD8 devices.
Table
4–1:
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
that have advanced features in Stratix
reconfiguring the PLL counter, clock frequency, and phase shift in real time, which
allows you to sweep PLL output frequencies and dynamically adjust the output clock
phase shift. The Quartus
external devices.
The chapter contains the following sections:
■
■
The global clock networks (GCLKs), regional clock networks (RCLKs), and periphery
clock networks (PCLKs) available in Stratix V devices are organized into hierarchical
clock structures. The clock networks provide up to 417 unique clock domains
(16 GCLKs + 92 RCLKs + 309 PCLKs) within the Stratix V device and allow up to 122
unique GCLK, RCLK, and PCLK clock sources (16 GCLKs + 23 RCLKs + 83 PCLKs)
per device quadrant.
Table 4–1
48 Single-ended (24 Differential)
56 Single-ended (28 Differential)
“Clock Networks in Stratix V Devices” on page 4–1
“Stratix V PLLs” on page 4–17
Number of Resources Available
228, 282, 306, and 309
lists the clock resources available in Stratix V devices.
108
16
92
39
or
4. Clock Networks and PLLs in Stratix V
®
II software enables the PLLs and their features without
(3)
(1)
(2)
®
DPA clock outputs, PLD-transceiver interface clocks,
V devices. It includes information about
CLK[0..27]p and CLK[0..27]n pins, PLL clock
CLK[0..27]p and CLK[0..27]n pins, PLL clock
CLK[0..23]p and CLK[0..23]n pins
CLK[0..27]p and CLK[0..27]n pins
Source of Clock Resource
outputs, and logic array
outputs, and logic array
I/O pins, and logic array
16 GCLKs + 23 RCLKs
16 GCLKs + 92 RCLKs
Devices
(1)
(2)
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