DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 211

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
Design Considerations
Design Considerations
May 2011 Altera Corporation
LVDS Direct Loopback Mode
I/O Bank Restrictions
1
LVDS direct loopback mode is available for true LVDS driver and receiver pairs in
the I/O module that have the same pad group number.
example of the LVDS direct loopback mode for I/O module 1 (RX1 and TX1) and I/O
module 2 (RX2 and TX2). The data comes in from the receiver pin through the true
LVDS input buffer and loops back to the true LVDS output buffer. You can use the
LVDS direct loopback mode to verify the RX and TX buffers by checking the
transmitted and received data.
LVDS direct loopback mode is not supported for LVDS driver and receiver pairs from
different I/O modules (for example, between RX1 and TX2).
Figure 5–22. LVDS Direct Loopback Path
To use the loopback mode, you must reset and recompile your existing design. The
Quartus II software generates an error if the specified I/O standard and pin direction
do not meet the requirements for direct loopback mode.
For an LVDS output pair already in use, you can apply the LVDS direct loopback
mode to override the connection from the device core with the signal from the true
differential input buffer in the same I/O module. Use this mode to observe the true
LVDS input signal of a completed design.
Although Stratix V devices feature various I/O capabilities for high-performance and
high-speed system designs, there are several other design considerations that require
your attention to ensure the success of your designs.
Each I/O bank can simultaneously support multiple I/O standards. The following
sections provide guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Stratix V devices.
RX1[p] RX1[n]
LVDS
In
R
Loopback
D
= 100 Ω
TX1[p] TX1[n]
To and From SERDES/DPA, PLL,
LVDS
Out
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
and FPGA Core
RX2[p]
LVDS
In
RX2[n]
Figure 5–22
R
Loopback
D
= 100 Ω
TX2[p] TX2[n]
shows a datapath
LVDS
Out
5–35