DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 254

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–10
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
1
1
Delay-Locked Loop
DQS phase-shift circuitry uses a DLL to dynamically control the clock delay required
by the DQS/CQ and CQn pin. In turn, the DLL uses a frequency reference to
dynamically generate control signals for the delay chains in each of the DQS/CQ and
CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are
Gray-coded to reduce jitter if the DLL updates the settings. If the DLL is in low jitter
mode, the phase-shift circuitry requires 2,560 clock cycles to lock and calculate the
correct input clock period. Otherwise, only 512 clock cycles are required. Altera
recommends not sending data during these clock cycles because there is no guarantee
that it will be captured properly. As the settings from the DLL may not be stable until
this lock period has elapsed, be aware that anything with these settings (including the
leveling delay system) may be unstable during this period.
You can still use the DQS phase-shift circuitry for any memory interfaces that are less
than 100 MHz. However, the DQS signal may not shift over 2.5 ns. Even if the DQS
signal is not shifted exactly to the middle of the DQ valid window, the IOE must be
able to capture the data in low-frequency applications, where a large amount of
timing margin is available.
There are a maximum of four DLLs in a Stratix V device, located in each corner of the
device. These four DLLs support a maximum of four unique frequencies, with each
DLL running at one frequency. Each DLL can have two outputs with different phase
offsets, which allows one Stratix V device to have eight different DLL phase shift
settings.
The DLL can access the two adjacent sides from its location within the device, if the
device has I/O banks on the side. For example, DLL_TR on the top right of the device
can access the top side (I/O banks 7A, 7B, 7C, 7D, 7E, 8A, 8B, 8C, 8D and 8E) and the
right side of the device (I/O banks 5A, 5B, 5C, 6A, 6B, and 6C), if the I/O banks are
available on the device. This means that each I/O bank is accessible by two DLLs,
giving more flexibility to create multiple frequencies and multiple-type interfaces.
You can have two different interfaces with the same frequency on the two sides
adjacent to a DLL, where the DLL controls the DQS delay settings for both interfaces.
Each bank can use settings from either or both adjacent DLLs. For example, DQS1R can
get its phase-shift settings from DLL_TR, while DQS2R can get its phase-shift settings
from DLL_BR.
If you are using leveling delay chains, you can only have one memory interface in
each I/O sub-bank (such as I/O sub-banks 5A, 5B, and 5C). This is because there is
only one leveling delay chain per I/O sub-bank.
The reference clock for each DLL may come from the PLL output clocks or clock input
pins.
resources for Stratix V devices.
Table 7–3
through
Table 7–6
list the available DLL reference clock input
Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
May 2011 Altera Corporation