DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 443
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 443 of 530
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Chapter 2: Transceiver Clocking in Stratix V Devices
FPGA Fabric-Transceiver Interface Clocking
May 2011 Altera Corporation
1
To achieve the clock resource savings, select a common clock driver for the transmitter
datapath interface of all identical transmitter channels.
identical channels clocked by a single clock (tx_clkout of channel 4). To clock eight
identical channels with a single clock, instantiate the tx_coreclkin port for all the
identical transmitter channels (tx_coreclkin[7:0]). Connect tx_clkout[4] to the
tx_coreclkin[7:0] ports. Also, connect tx_clkout[4] to the transmitter data and
control logic for all eight channels.
Resetting or powering down channel 4 will lead to a loss of the clock for all eight
channels.
Figure 2–20. Eight Identical Channels with a Single User-Selected Transmitter Interface Clock
The common clock must have a 0 PPM difference with respect to the read side of the
TX FIFO (in the 10G PCS channel) or TX phase compensation FIFO (in the standard
PCS channel) of all the identical channels. A frequency difference causes the FIFO to
under-run or overflow, depending on whether the common clock is slower or faster,
respectively. You can drive the 0 PPM common clock by one of the following sources:
■
■
■
tx_clkout of any channel in non-bonded channel configurations
tx_clkout[0] in bonded channel configurations
Dedicated refclk pins
Channel [7:0] Transmitter
Data and Control Logic
FPGA Fabric
tx_coreclkin[7]
tx_coreclkin[6]
tx_coreclkin[5]
tx_coreclkin[4]
tx_coreclkin[2]
tx_coreclkin[1]
tx_coreclkin[0]
tx_coreclkin[3]
tx_clkout[4]
Stratix V Device Handbook Volume 3: Transceivers
Figure 2–20
Transceivers
Channel 7
Channel 6
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
Channel 0
shows eight
2–27
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