DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 467

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Interlaken
May 2011 Altera Corporation
1
Block Synchronization
The block synchronizer in the receiver PCS achieves and maintains a 64B/67B word
boundary lock. This block searches for valid synchronization header bits within the
data stream and achieves lock after 64 consecutive legal synchronization patterns are
found. After a 64B/67B word boundary lock is achieved, it continuously monitors
and flags for invalid synchronization header bits. If 16 or more invalid
synchronization header bits are found within 64 consecutive word boundaries, the
block synchronizer de-asserts the lock state and searches again for valid
synchronization header bits.
The block synchronizer implements the flow diagram shown in Figure 13 of
Interlaken Protocol Definition v1.2 and provides the word lock status to the FPGA
fabric.
64B/67B Framing
The frame generator implements 64B/67B encoding as explained in Interlaken
Protocol Definition v1.2, and maps the transmit data into metaframes. The metaframe
length is programmable from 5 to a maximum value of 8191, 8-byte words.
Ensure that the metaframe length is programmed to the same value for both the
transmitter and receiver.
The frame synchronizer delineates the metaframe boundaries and searches for each of
the framing layer control words: Synchronization, Scrambler State, Skip, and
Diagnostic. When four consecutive synchronization words have been identified, the
frame synchronizer achieves the frame locked state. Subsequent metaframes are then
checked for valid synchronization and scrambler state words. If four consecutive
invalid synchronization words or three consecutive mismatched scrambler state
words are received, the frame synchronizer loses frame lock. In addition, the frame
synchronizer provides a receiver metaframe lock status to the FPGA fabric.
Running Disparity
The disparity generator inverts the sense of bits in each transmitted word to maintain
a running disparity of ± 96 bit boundary. It supplies a framing bit in bit position 66 as
explained in Table 4 of Interlaken Protocol Definition Revision 1.2. The framing bit
enables the disparity checker to identify whether the bits for that word are inverted.
Frame Synchronous Scrambling/Descrambling
The scrambler/descrambler block in the transmitter/receiver PCS implements the
scrambler/descrambler polynomial x
Revision 1.2. synchronization and scrambler state words, as well as the 64B/67B
framing bits are not scrambled/descrambled. The Interlaken PHY IP core
automatically programs random linear feedback shift register (LFSR) initialization
seed values per lane.
The receiver PCS synchronizes the scrambler with the metaframe as described in the
state flow shown in Figure 1 of Interlaken Protocol Definition Revision 1.2.
58
+ x
39
+ 1 per Interlaken Protocol Definition
Stratix V Device Handbook Volume 3: Transceivers
4–11