DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 200

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–24
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Serial Data Transfer
After you complete calibration, you must serially shift out the 32-bit OCT calibration
codes (16-bit R
corresponding I/O buffers. Only one OCT calibration block can send out the codes at
any time by asserting only one ENASER[N] signal at a time. After you deassert ENAOCT,
wait at least one OCTUSRCLK cycle to enable any ENASER[N] signal to begin serial
transfer. To shift the 32-bit code from the OCT calibration block[N], you must assert
ENASER[N] for exactly 32 OCTUSRCLK cycles. Between two consecutive asserted ENASER
signals, there must be at least one OCTUSRCLK cycle gap (refer to
Figure 5–11. OCT User Mode Signal—Timing Waveform for One OCT Block
Note to
(1) t
After calibrated codes are shifted in serially to each I/O bank, the calibrated codes
must be converted from serial to parallel format before being used in the I/O buffers.
Figure 5–11
calibration codes in each I/O bank. All I/O banks that received the codes from the
same OCT calibration block can have S2PENA asserted at the same time, or at a
different time, even while another OCT calibration block is calibrating and serially
shifting codes. The S2PENA signal is asserted one OCTUSRCLK cycle after ENASER is
deasserted for at least 25 ns. You cannot use I/Os for transmitting or receiving data
when their S2PENA is asserted for parallel codes transfer.
s2p
Figure
 25 ns.
OCTUSRCLK
S2PENA_1A
nCLRUSR
ENASER0
ENAOCT
5–11:
shows the S2PENA signals that can be asserted at any time to update the
S
OCT and 16-bit R
1000 OCTUSRCLK Cycles
Calibration Phase
T
OCT) from each OCT calibration block to the
Chapter 5: I/O Features in Stratix V Devices
OCTUSRCLK
Cycles
32
t s2p
Figure
May 2011 Altera Corporation
(1)
5–11).
OCT Calibration