DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 304

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–24
Figure 9–11. Connection Setup for Programming the EPCS Device Using the JTAG Interface
Notes to
(1) Connect the pull-up resistors to V
(2) Resistor value can vary from 1 k
(3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer to
(4) Instantiate SFL in your design to form a bridge between the EPCS device and the Stratix V device. For more information about SFL, refer to
(5) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
370: Using the Serial Flash Loader with the Quartus II
is 100 MHz.
Figure
9–11:
f
EPCS Device
For more information about SRunner software driver, refer to
Embedded Solution for Serial Configuration Device
In-system programming offers you an option to program the EPCS or EPCQ device
either using an AS programming interface or a JTAG interface. Using the AS
programming interface, the configuration data is programmed into the EPCS by the
Quartus II software or any supported third-party software. Using the JTAG interface,
an Altera IP called Serial Flash Loader (SFL) must be downloaded into the Stratix V
device to form a bridge between the JTAG interface and the EPCS or EPCQ device.
This allows the EPCS or the EPCQ device to be programmed directly using the JTAG
interface.
Figure 9–11
the JTAG interface.
DATA
DCLK
ASDI
nCS
V

CCPGM (1)
CCPGM
to 10 k
10 kΩ
shows the connection setup when programming the EPCS device using
and V

V
. Perform signal integrity analysis to select the resistor value for your setup.
CCPGM (1)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
CCPD
10 kΩ
at a 3.0-V supply.
(3)
(5)
Software.
GND
V
CCPGM (1)
10 kΩ
AS_DATA1
DCLK
nCSO
ASDO
MSEL[4..0]
CLKUSR
nSTATUS
CONF_DONE
nCONFIG
nCE
Stratix V Device
Loader
Serial
Flash
(4)
TDO
TMS
TCK
TDI
V
(2)
CCPD (1)
Active Serial Configuration (Serial Configuration Devices)
Programming.
V
CCPD (1)
1 kΩ
(2)
GND
(JTAG Mode) (Top View)
Pin 1
10-Pin Male Header
Download Cable
AN 418: SRunner: An
May 2011 Altera Corporation
V
Table 9–4 on page
CCPD (1)
GND
9–7.
AN