DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 489

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
GIGE
Figure 4–22. Automatic Ordered Set Generation
Figure 4–23. Reset Condition in GIGE Mode
May 2011 Altera Corporation
tx_digitalreset
tx_dataout
Ordered Set
tx_datain [ ]
clock
tx_dataout
Figure 4–22
Reset Condition
After assertion of tx_ready after reset, the GIGE transmitter automatically transmits
three /K28.5/ comma code groups before transmitting user data on the
tx_parallel_data[7:0] and tx_datak port. This could affect the synchronization
state machine behavior at the receiver.
Depending on when you start transmitting the synchronization sequence, there could
be an even or odd number of /Dx.y/ code groups transmitted between the last of the
three automatically sent /K28.5/ code groups and the first /K28.5/ code group of the
synchronization sequence. If there is an even number of /Dx.y/ code groups received
between these two /K28.5/ code groups, the first /K28.5/ code group of the
synchronization sequence begins at an odd code group boundary (rx_even = FALSE).
An IEEE802.3-compliant GIGE synchronization state machine treats this as an error
condition and goes into the loss of sync state.
Figure 4–23
automatically sent /K28.5/ and the first user-sent /K28.5/. The first user-sent
/K28.5/ code group received at an odd code group boundary in cycle n + 3 takes the
receiver synchronization state machine in the loss of sync state. The first
synchronization ordered set /K28.5/Dx.y/ in cycles n + 3 and n + 4 is discounted and
three additional ordered sets are required for successful synchronization.
Synchronization
The word aligner in GIGE functional mode is configured in automatic
synchronization state machine mode. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization when the
receiver receives three consecutive synchronization ordered sets. A synchronization
ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code
groups. The fastest way for the receiver to achieve synchronization is to receive three
continuous {/K28.5/, /Dx.y/} ordered sets.
clock
K28.5
K28.5
Dx.y
xxx
shows the automatic idle ordered set generation.
shows an example of even numbers of /Dx.y/ between the last
K28.5
D14.3
K28.5
K28.5
/I1/
K28.5
D5.6
K28.5
n
D24.0
K28.5
n + 1
Dx.y
/I2/
n + 2
Dx.y
K28.5
D16.2
n + 3 n + 4
K28.5
D15.8
K28.5
Dx.y
/I2/
Stratix V Device Handbook Volume 3: Transceivers
K28.5
D16.2
K28.5
Dx.y
D21.5
K28.5
/C1/
K28.5
D21.5
Dx.y
Dx.y
4–33