DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 462

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–6
Stratix V Device Handbook Volume 3: Transceivers
Block Synchronization
The block synchronizer in the receiver PCS determines when the receiver has
obtained lock to the received data stream. It implements the lock state diagram shown
in Figure 49-12 of the IEEE 802.3-2008 specification.
The block synchronizer provides a status signal to indicate whether it has achieved
block synchronization or not.
Self-Synchronous Scrambling/Descrambling
The scrambler/descrambler blocks in the transmitter/receiver PCS implements the
self-synchronizing scrambler/descrambler polynomial 1 + x39 + x58 as described in
clause 49 of the IEEE 802.3-2008 specification. The scrambler/descrambler blocks are
self-synchronizing and do not require an initialization seed. Barring the two sync
header bits in each 66-bit data block, the entire payload is scrambled or descrambled.
BER Monitor
The BER monitor block in the receiver PCS implements the BER monitor state
diagram shown in Figure 49-13 of the IEEE 802.3-2009 specification. The BER monitor
provides a status signal to the MAC whenever the link BER threshold is violated.
The 10GBASE-R PHY IP core provides a status flag to indicate a high BER whenever
16 synchronization header errors are received within a 125 s window.
Clock Compensation
The receiver FIFO in the receiver PCS datapath is designed to compensate up to
±100 PPM difference between the remote transmitter and the local receiver. It does so
by inserting Idles (/I/), and deleting Idles (/I/) or Ordered Sets (/O/) depending on
the PPM difference.
Idle Insertion
Idle (/I/) or Sequence Ordered Set (/O/) Deletion
■
■
The receiver FIFO inserts eight /I/ codes following an /I/ or /O/ to compensate
for clock rate disparity.
The receiver FIFO deletes either four /I/ codes or ordered sets (/O/) to
compensate for the clock rate disparity. It implements the following
IEEE802.3-2008 deletion rules:
Deletes four /I/ codes if the most significant 32-bits of the preceding word do
not contain a Terminate /T/ control character.
Deletes one /O/ ordered set only when it receives two consecutive /O/
ordered sets.
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
May 2011 Altera Corporation
10GBASE-R