DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 242

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
6–28
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
2.
Figure 6–26. Input Time Delay Assignment Through TimeQuest Timing Analyzer
3. Click the Browse button to the right of the Targets option. You can view a list of all
Figure 6–27. Name Finder Window in Set Input Delay Option
4. Select the LVDS receiver serial input ports (from the list) according to the input
Figure 6–26
clock name must reference the source synchronous clock that feeds the LVDS
receiver. Select the desired clock using the pull-down menu.
available ports using the List option in the Name Finder window
delay you set. Click OK.
shows the setting parameters for the Set Input Delay option. The
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Source-Synchronous Timing Budget
May 2011 Altera Corporation
(Figure
6–27).

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