DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 517

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Standard PCS Custom and Low Latency Configurations
Figure 5–13. Standard PCS Low Latency Datapath
May 2011 Altera Corporation
Fabric
FPGA
Low Latency Using the Standard PCS Datapath
A Low Latency PHY IP core using the standard PCS is available for 8-bit, 10-bit,
16-bit, or 20-bit PCS data width configurations.
transmitter and receiver channel PCS blocks if you use the Low Latency PHY IP core.
The low latency PCS datapath consists of the following blocks:
■
■
Table 5–4
single-width and double-width modes.
Table 5–4. PCS-PMA Interface Widths and Data Rates
In low latency PCS configurations, the TX and RX phase compensation FIFOs are
always enabled. Depending on the targeted data rate, you can optionally bypass the
byte serializer and deserializer blocks.
Transmitter channel PCS
■
■
Receiver channel PCS
■
■
TX phase compensation FIFO
Byte serializer
RX phase compensation FIFO
Byte deserializer
Low latency 16-bit or 20-bit width
lists the PCS and PMA interface widths and data rates in custom
Low Latency PHY IP Core
Low latency 10-bit width
Low latency 8-bit width
Byte Serializer
Transmitter PCS
Receiver PCS
8B/10B Encoder
Figure 5–13
Stratix V Device Handbook Volume 3: Transceivers
Supported Data Rate Range PMA
600 Mbps to 4.0 Gbps
600 Mbps to 5.0 Gbps
Slip
TX
Bit
1 Gbps to 8.5 Gbps
shows the available
Transmitter PMA
Receiver PMA
5–15