DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 281

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
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SV51010-1.3
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
May 2011
May 2011
SV51010-1.3
This chapter contains information about the Stratix
schemes, instructions about how to execute the required configuration schemes, and
all the necessary option pin settings. This chapter also reviews the different ways you
can configure your device and explains the design security and remote system
upgrade features for the Stratix V devices.
This chapter includes the following sections:
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Stratix V devices use SRAM cells to store configuration data. Because SRAM memory
is volatile, you must download the configuration data to the Stratix V device each
time the device powers up. You can configure Stratix V devices using one of four
configuration schemes:
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All configuration schemes use either an external controller (for example, a MAX
device or microprocessor), a configuration device, or a download cable. For more
information about the configuration features, refer to
page
“Configuration Features” on page 9–2
“Power-On Reset Circuit and Configuration Pins Power Supply” on page 9–2
“Configuration Sequence” on page 9–4
“Configuration Schemes” on page 9–7
“Fast Passive Parallel Configuration” on page 9–9
“Active Serial Configuration (Serial Configuration Devices)” on page 9–16
“Passive Serial Configuration” on page 9–28
“JTAG Configuration” on page 9–34
“Device Configuration Pins” on page 9–38
“Configuration Data Decompression” on page 9–42
“Remote System Upgrades” on page 9–44
“Design Security” on page 9–53
Fast passive parallel (FPP) (×8, ×16, and ×32)
Active serial (AS) (×1 and ×4)
Passive serial (PS)
JTAG
9–2.
9. Configuration, Design Security, and
Remote System Upgrades in Stratix V
®
V supported configuration
“Configuration Features” on
Devices
Subscribe
®
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