DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 492
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
- Current page: 492 of 530
- Download datasheet (16Mb)
4–36
Stratix V Device Handbook Volume 3: Transceivers
Table 4–7
Table 4–7. Transceiver Datapath Clock Frequencies in GIGE Mode
Transceiver Channel Placement Guidelines
There are no specific placement constraints when placing a GIGE transceiver channels
in a transceiver bank. Up to five GIGE channels may be placed on channels 0, 2, 3, 5,
and either channel 1 or channel 4 when using the CMU PLL; Up to six GIGE channels
may be placed anywhere on one of the six transceiver channels per bank when using
the ATX PLL.
the CMU PLL or the ATX PLL to drive the GIGE link. If a CMU PLL is implemented,
channel 1 or channel 4 in a transceiver bank generates the transmitter serial clock to
drive the ×1 clock lines for up to five GIGE channels per transceiver bank. If an ATX
PLL is implemented, the ATX PLL generates the transmitter serial clock to drive the
×1 clock lines for up to six GIGE channels per transceiver bank.
Functional
Mode
GIGE
lists the transceiver datapath clock frequencies in GIGE functional mode.
Figure 4–27
Data Rate
1.25 Gbps
Line
High-Speed Serial
shows the allowed channel placement when using either
Clock Frequency
Half-Rate
625 MHz
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Fabric-Transceiver
Interface Width
1-bit control
8-bit data,
FPGA
FPGA Fabric-Transceiver
May 2011 Altera Corporation
Interface Clock
Frequency
125 MHz
GIGE
Related parts for DK-DEV-5SGXEA7/ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: