DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 352

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

11–2
Figure 11–1. HSSI Transmitter BSC with IEEE Std. 1149.6 BST Circuitry for Stratix V Devices
Figure 11–2. HSSI Receiver/Input Clock Buffer BSC with IEEE Std. 1149.6 BST Circuitry for Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
HIGHZ
MEM_INIT
SDIN SHIFT
SDIN
0
0
1
1
Figure 11–1
Figure 11–2
SHIFT
0
0
0
1
1
1
Capture
D
D
CLK
D
D
D
Capture
CLK
Q
Q
Registers
Q
Q
Q
UPDATE
shows the Stratix V HSSI transmitter BSC.
shows the Stratix V HSSI receiver/input clock buffer BSC.
Registers
Update
UPDATE
Update
D
D
D
MODE
Q
Q
Q
AC_TEST
HIGHZ
BSRX1
BSOUT1
BSRX0
BSOUT0
MODE
AC_TEST
MEM_INIT
AC_MODE
BSCAN
0
1
AC_MODE
Chapter 11: JTAG Boundary-Scan Testing in Stratix V Devices
BSCAN
1
0
0
1
BSOEB
MORHZ
Optional INTEST/RUNBIST
PMA
not supported
Hysteretic
Hysteretic
(DATAIN)
Memory
Memory
Mission
PMA
BSTX1
BSTX0
ACJTAG_BUF_OE
OE Logic
(DATAOUT)
TX_BUF_OE
Mission
IEEE Std. 1149.6 Boundary-Scan Register
AC JTAG Test
AC JTAG Test
Receiver
Receiver
nOE
May 2011 Altera Corporation
OE
OE
AC JTAG
AC JTAG
Output
Output
Buffer
Buffer
Tx Output
Buffer
Rx Input
Buffer
Pad
Pad
Pad
Pad