DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 355

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 11: JTAG Boundary-Scan Testing in Stratix V Devices
I/O Voltage Support in a JTAG Chain
I/O Voltage Support in a JTAG Chain
May 2011 Altera Corporation
1
1
If the device is in reset state, when the nCONFIG or nSTATUS signal is low, the device
IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue
the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high.
IEEE Std. 1149.6 mandates the addition of two new instructions—EXTEST_PULSE and
EXTEST_TRAIN. These two instructions enable edge-detecting behavior on the signal
path containing the HSSI pins. These instructions implement new test behaviors for
the HSSI pins and simultaneously behave identically to the IEEE Std. 1149.1 EXTEST
instruction for non-HSSI pins.
If you use DC coupling on the HSSI signals, execute the EXTEST instruction. If you use
AC coupling on the HSSI signals, execute the EXTEST_PULSE instruction.
A device operating in BST mode uses four required pins—TDI, TDO, TMS, TCK, and one
optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI,
TMS, and TRST pins have internal weak pull-up resistors. The TDO output pin and all
the JTAG input pins are powered by the 2.5-V/3.0-V V
All user I/O pins are tri-stated during JTAG configuration.
The JTAG chain can support several different devices. However, use caution if the
chain contains devices that have different V
TDO pin must meet the specification of the TDI pin it drives.
Table 11–3
operation.
Table 11–3. Supported TDO and TDI Voltage Combinations
Stratix V
Non-Stratix V
Notes to
(1) The TDO output buffer meets V
(2) The TDO output buffer meets V
(3) Input buffer must be 3.0-V tolerant.
(4) Input buffer must be 2.5-V tolerant.
Device
Table
lists board design recommendations to ensure proper JTAG chain
11–3:
V
V
V
V
V
V
CCPD
CCPD
CC
CC
CC
CC
TDI Input Buffer
= 3.3 V
= 2.5 V
= 1.8 V
= 1.5 V
OH
OH
= 3.0 V
= 2.5 V
(MIN) = 2.4 V.
(MIN) = 2.0 V.
Power
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CCIO
V
CCPD
levels. The output voltage level of the
v
v
v
v
= 3.0 V
v
v
(3)
(3)
(3)
(3)
CCPD
Stratix V TDO V
(1)
supply of I/O bank 3A.
V
CCPD
CCPD
v
v
v
v
= 2.5 V
v
v
(4)
(4)
(4)
(4)
(2)
11–5