DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 419
DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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Chapter 2: Transceiver Clocking in Stratix V Devices
Input Reference Clocking
Figure 2–3. Input Reference Clock Sources for Transceiver Channels in a Transceiver Bank
Note to
(1) N = number of transceiver channels on a side divided by 3, which is equal to the number of dedicated refclk pins.
May 2011 Altera Corporation
Fractional PLL
Fractional PLL
Figure
Reference Clocks Driven
by the Fractional PLLs
2–3:
2
2
2
2
2
2
Figure 2–3
Dedicated refclk Pins
Stratix V devices have one dedicated refclk pin for each group of three transceiver
channels. Every dedicated reference clock pin drives a clock network spanning the
side of the device.
Dedicated refclk Pins Using the Reference Clock Network
Each dedicated refclk pin can drive any transmit PLL on the same side of the device
through the reference clock network. Designs using multiple transmit PLLs that
require the same reference clock frequency and are located along the same side of the
device can share the same dedicated refclk pin.
ATX
PLL
ATX
PLL
shows the input reference clock sources for a transceiver bank.
2
2
Reference Clock
N
N
Network
N (1)
N
N
N
N
N
N
Stratix V Device Handbook Volume 3: Transceivers
Fractional PLL Clock and Reference Clocks Driven
by the Fractional PLLs
Dedicated refclk and Reference Clock Network
Reference Clock Network
Clocks
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Channel
Channel
Channel
Channel
Channel
Channel
Channel PLL
Channel PLL
Channel PLL
Channel PLL
Channel PLL
Channel PLL
Dedicated
refclk
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Dedicated
refclk
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
2–3
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