DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 238

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–24
Figure 6–23. Bit-Order and Word Boundary for One Differential Channel
Note to
(1) These are only functional waveforms and are not intended to convey timing information.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Transmitter Channel
Operation (x8 Mode)
Operation (x8 Mode)
Receiver Channel
rx_out [7..0]
tx_outclock
rx_outclock
rx_inclock
Figure
tx_out
rx_in
6–23:
X
7
X X X X X X X
6
X X X X X X X X
For other serialization factors, use the Quartus II software tools to find the bit position
within the word. The bit positions after deserialization are listed in
Table 6–6
The MSB and LSB positions increase with the number of channels used in a system.
Table 6–6. Differential Bit Naming
5
Receiver Channel Data Number
Previous Cycle
4
3
2
lists the conventions for differential bit naming for 18 differential channels.
1
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
MSB
7
X
6
X
Current Cycle
5
X X X X X X X X
X
4 3
X
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
X
2
X
1
LSB
X
0
X X X
X
MSB Position
Next Cycle
X
X
103
111
119
127
135
143
15
23
31
39
47
55
63
71
79
87
95
7
(Note 1)
X X X X 7 6 5 4
X X X X X
X
Internal 8-Bit Parallel Data
X
X
X
X
X
Source-Synchronous Timing Budget
X
May 2011 Altera Corporation
X
X
LSB Position
Table
3 2 1 0 X X X X
X
104
112
120
128
136
16
24
32
40
48
56
64
72
80
88
96
0
8
X
6–6.
X
X
X