DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 497

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
XAUI
May 2011 Altera Corporation
Stratix V transceivers in a XAUI configuration do not support the XGMII interface to
the MAC/RS as defined in IEEE 802.3-2008 specification. Instead, they allow the
transferring of 16-bit data and 2-bit control code on each of the four XAUI lanes, only
at the positive edge (SDR) of the 156.25 MHz interface clock, as shown in
Figure 4–31. Implementation of the XGMII Specification in Stratix V Devices
8B/10B Encoding/Decoding
Each of the four lanes in a XAUI configuration support an independent 8B/10B
encoder/decoder as specified in Clause 48 of the IEEE802.3-2008 specification.
8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial
data stream to five, thereby ensuring DC balance as well as enough transitions for the
receiver CDR to maintain a lock to the incoming data.
The XAUI PHY IP core provides status signals to indicate running disparity as well as
the 8B/10B code group error.
Transmitter and Receiver State Machines
In a XAUI configuration, the Stratix V transceivers implement the transmitter and
receiver state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008
specification.
Stratix V Transceiver Interface (SDR)
Interface Clock (156.25 MHz)
Interface Clock (156.25 MHz)
XGMII Transfer (DDR)
Lane 0
Lane 1
Lane 2
Lane 3
Lane 0
Lane 1
Lane 2
Lane 3
8-bit
D0
D0
D0
D0
{D1, D0}
{D1, D0}
{D1, D0}
{D1, D0}
16-bit
D1
D1
D1
D1
D2
D2
D2
D2
{D3, D2}
{D3, D2}
{D3, D2}
{D3, D2}
Stratix V Device Handbook Volume 3: Transceivers
D3
D3
D3
D3
Figure
4–31.
4–41