DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 526
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DK-DEV-5SGXEA7/ES
Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Specifications of DK-DEV-5SGXEA7/ES
Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
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6–4
Reverse Serial Pre-CDR Loopback
Figure 6–4. Reverse Serial Pre-CDR Loopback Datapath
Note to
(1) Grayed-out blocks are not active in this configuration.
Document Revision History
Table 6–1. Document Revision History
Stratix V Device Handbook Volume 3: Transceivers
May 2011
December 2010
July 2010
Fabric
FPGA
Figure
Date
6–4:
Compensation
wrclk
TX Phase
Version
FIFO
Reverse serial pre-CDR loopback is available as a subprotocol under custom
configuration. In reverse serial pre-CDR loopback, the data received through the
rx_serial_data port is looped back to the tx_serial_data port before the receiver
CDR. The received data is also available to the FPGA logic.
transceiver channel datapath for reverse serial pre-CDR loopback mode.
The active block of the transmitter channel is only the transmitter buffer. You can
change the V
Manager. The pre-emphasis settings for the transmitter buffer cannot be changed in
this configuration.
Table 6–1
2.0
1.1
1.0
rdclk
■
■
■
■
■
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
Added the
Updated
Updated the chapter title.
Chapter moved to Volume 3.
Minor text edits.
lists the revision history for this chapter.
OD
wrclk
Byte Serializer
on the transmitter buffer through the ALTGX MegaWizard Plug-In
Figure
“Reverse Serial Loopback”
Transmitter PCS
Receiver PCS
rdclk
6–2.
(Note 1)
8B10B Encoder
Chapter 6: Transceiver Loopback Support in Stratix V Devices
and
Changes
“Reverse Serial Pre-CDR Loopback”
Reverse Parallel
Loopback Path
Figure 6–4
Reverse Serial Pre-CDR Loopback
May 2011 Altera Corporation
Transmitter PMA
Receiver PMA
shows the
sections.
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