DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 22

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–16
Table 1–11. Complex Multiplication with Variable Precision DSP Blocks
Stratix V Device Handbook
Multiplier Size (bits)
18×18
18×25
18×36
27×27
Complex multiplication is common in DSP algorithms. One of the most popular
applications of complex multipliers is the fast Fourier transform (FFT) algorithm. This
algorithm has the characteristic of increasing precision requirements on only one side
of the multiplier. The variable precision DSP block is designed to support this with a
proportional increase in DSP resources with precision growth.
complex multiplication with variable precision DSP blocks.
Additionally, for FFT applications with high dynamic range requirements, only the
Altera
implementation, with the resource usage and performance similar to high-precision
fixed point implementations.
Other new features include:
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The variable precision DSP block is ideal for higher bit precision in high-performance
DSP applications. At the same time, it can efficiently support the many existing 18-bit
DSP applications, such as high definition video processing and remote radio heads.
Stratix V FPGAs, with the variable precision DSP block architecture, are the only
FPGA family that can efficiently support many different precision levels, up to and
including floating point implementations. This flexibility results in increased system
performance, reduced power consumption, and reduced architecture constraints on
system algorithm designers.
64-bit accumulator, the largest in the industry
Hard pre-adder, available in both 18- and 27-bit modes
Cascaded output adders for efficient systolic FIR filters
Internal coefficient register banks
Enhanced independent multiplier operation
Efficient support for single- and double-precision floating point arithmetic
Ability to infer all the DSP block modes through HDL code using the Quartus II
design suite.
2 Variable Precision DSP Blocks
3 Variable Precision DSP Blocks
4 Variable Precision DSP Blocks
4 Variable Precision DSP Blocks
®
FFT MegaCore offers an option of single precision floating point
DSP Block Resources
Accommodate bit growth through FFT stages
Single precision floating point
Highest precision FFT stages
Resource optimized FFTs
Chapter 1: Stratix V Device Family Overview
Expected Usage
Table 1–11
June 2011 Altera Corporation
Variable Precision DSP Block
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