DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 478

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–22
Table 4–5. PIPE Configuration Channel Placement
Stratix V Device Handbook Volume 3: Transceivers
Notes to
(1) Placement by the Quartus II software may vary with design, thus resulting in higher channel usage.
Configuration
Table
×1
×4
×8
Transceiver Clocking and Channel Placement Guidelines
4–5:
1
Any channel
Contiguous channels
Contiguous channels
This section describes the transceiver clocking and channel placement guidelines for
PIPE configurations.
For PIPE Gen1 configurations, ATX PLL is currently not supported for 100 MHz
reference clock.
Transceiver Channel Placement Guidelines
Table 4–5
configurations. The Quartus II software automatically places the CMU PLL in a
channel different from that of the data channels.
For PIPE ×1 configurations, the channel can be placed anywhere within a transceiver
bank that contains the transmit PLL.
channel placement for PIPE ×4 and ×8 configurations.
Data Channel Placement
lists the physical placement of PIPE channels in ×1, ×4, and ×8 bonding
Channel Utilization Using
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Figure 4–14
CMU PLL
2
5
9
(1)
and
Figure 4–15
PCI Express (PCIe)—Gen1 and Gen2
May 2011 Altera Corporation
Channel Utilization Using
show examples of
ATX PLL
1
4
8
(1)