DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 124

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

3–8
Table 3–3. Functions Supported by Accumulator in Stratix V Devices
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Zeroing
Preload
Accumulation
Decimation
Multipliers
Adder and Accumulator
Systolic Register
Function
There are two multipliers (Mult_H and Mult_L) per variable precision DSP block. You
can configure these two multipliers to work as a 27 x 27 multiplier, two 18 x 18
multipliers, or three 9 x 9 multipliers, depending on the operational mode. A single
variable precision DSP block can perform many multiplications in parallel, depending
on the data width of the multiplier. For more information, refer to
Descriptions” on page
The Stratix V variable precision DSP block supports a 64-bit adder and 64-bit
accumulator. You can use the 64-bit adder as a full 64-bit adder or several small
adders with various sizes, depending on the operational mode.
Table 3–3
You can dynamically control the function of the accumulator by three control
signals—NEGATE, LOADCONST, and ACCUMULATE.
signals control the accumulator functions.
Table 3–4. Dynamic Control Signals for 64-Bit Accumulator for Stratix V Devices
There are two systolic registers per variable precision DSP block. The first systolic
register has two 18-bit registers that are used to register the Mult_L’s two 18-bit
inputs. You must clock these registers with the same clock source as the multiplier
inputs. The second systolic register is a 44-bit register that is used to delay the
chainout output to the next variable precision DSP block. You must clock this register
with the same clock source as the output register bank. If the variable precision DSP
block is not configured in systolic FIR mode, both systolic registers are bypassed.
Accumulate
Disables the accumulator.
Loads an initial value to the accumulator. Only 1 bit of the 64-bit preload value can be “1”. It
can be used as rounding the DSP result to any position of the 64-bit result.
Adds the current result to the previous accumulate result.
This function takes the current result, converts it into two’s compliment, and adds it to the
previous result.
Decimate
Function
Preload
Zero
lists the functions supported by the accumulator in Stratix V devices.
3–9.
NEGATE
0
0
1
0
Chapter 3: Variable Precision DSP Blocks in Stratix V Devices
Description
Table 3–4
LOADCONST
Variable Precision DSP Block Resource Descriptions
0
0
0
1
lists how these dynamic
May 2011 Altera Corporation
“Operational Mode
ACCUMULATE
0
1
1
0