DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 381

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
PMA Architecture
May 2011 Altera Corporation
f
1
1
Programmable Differential On-Chip Termination
The receiver buffers support optional differential OCT resistances of 85, 100, 120, and
150  . To select the desired receiver OCT resistor, make the assignments shown in
Table 1–1
Table 1–1. Receiver On-Chip Termination Assignment Settings for Stratix V Devices
The receiver OCT resistors have calibration support to compensate for process,
voltage, and temperature (PVT) variations.
Programmable V
The receiver buffers have on-chip biasing circuitry to establish the required V
receiver input. It supports V
On-chip biasing circuitry is effective only if you select on-chip receiver termination.
If you select external termination, you must implement off-chip biasing circuitry to
establish the V
Signal Threshold Detection Circuitry
In a PCIe configuration, you can enable the optional signal threshold detection
circuitry. If enabled, this option senses whether the signal level present at the receiver
input buffer is above the signal detect threshold voltage that you specified.
For more information, refer to the
Offset Cancellation in the Receiver Buffer and Receiver CDR
As silicon progresses towards smaller process nodes, the performance of circuits at
these smaller nodes depends more on process variations. These process variations
result in analog voltages that can be offset from the required ranges. Offset
cancellation logic corrects these offsets. The receiver buffer and receiver CDR require
offset cancellation.
Receiver Analog Settings
This section describes programmable equalization and DC gain, which you can
change to improve the signal integrity (SI).
Programmable Equalization
Each receiver buffer has five independently programmable tap equalization circuits
that boost the high-frequency gain of the incoming signal, thereby compensating for
the low-pass filter effects of the physical medium. The amount of high-frequency gain
required depends on the loss characteristics of the physical medium. The equalization
circuitry provides up to 20 dB of high-frequency boost.
Assignment Name
Available Values
in the Quartus II Assignment Editor.
Assign To
CM
CM
at the receiver input buffer.
CM
Input Termination
OCT 85
settings of 0.82 V and 1.1 V.
Altera Transceiver PHY IP Core User
 , OCT 100  , OCT 120  , OCT 150  , OFF
rx_serial_data (Receiver Input Data Pins)
Stratix V Device Handbook Volume 3: Transceivers
Guide.
CM
at the
1–9