DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 262

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–18
Figure 7–7. DQS Update Enable Waveform
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
(Updated every 8 cycles)
DQS Delay Settings
Update Enable
Circuitry Output
System Clock
DLL Counter Update
(Every 8 cycles)
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input
DQS/CQ and CQn signals to be shifted by the amount specified by the DQS
phase-shift circuitry or the logic array. There are four delay elements in the DQS delay
chain; the first delay chain closest to the DQS/CQ pin is shifted either by the DQS
delay settings or by the sum of the DQS delay setting and the phase-offset setting. The
number of delay chains required is transparent because the UniPHY megafunction
automatically sets it when you choose the operating frequency. The DQS delay
settings can come from the DQS phase-shift circuitry on either end of the I/O banks or
from the logic array.
The delay elements in the DQS logic block have the same characteristics as the delay
elements in the DLL. When the DLL is not used to control the DQS delay chains, you
can input your own Gray-coded 7-bit settings using the delayctrlin[6..0] signals
available in the UniPHY megafunction. These settings control 1, 2, 3, or all 4 delay
elements in the DQS delay chains. The UniPHY megafunction can also dynamically
choose the number of DQS delay chains required for the system. The amount of delay
is equal to the sum of the intrinsic delay of the delay element and the product of the
number of delay steps and the value of the delay steps.
You can also bypass the DQS delay chain to achieve a 0° phase shift.
Update Enable Circuitry
Both the DQS delay settings and the phase-offset settings pass through a register
before going into the DQS delay chains. The registers are controlled by the update
enable circuitry to allow enough time for any changes in the DQS delay setting bits to
arrive at all the delay elements. This allows them to be adjusted at the same time. The
update enable circuitry enables the registers to allow enough time for the DQS delay
settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic
blocks before the next change. It uses the input reference clock or a user clock from the
core to generate the update enable output. The UniPHY megafunction uses this circuit
by default.
output.
Figure 7–7
shows an example waveform of the update enable circuitry
7 bit
Chapter 7: External Memory Interfaces in Stratix V Devices
DLL Counter Update
(Every 8 cycles)
Stratix V External Memory Interface Features
May 2011 Altera Corporation