DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 194

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–18
Table 5–11. Selectable I/O Standards for OCT With and Without Calibration (Part 2 of 2)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Differential HSTL 1.2 Class II
Differential SSTL15
Differential SSTL135
Differential SSTL125
Differential SSTL12
Differential HSUL 1.2
Notes to
(1) The 25-and 50- driver impedance are calibrated with the RZQ pin connected to a 100- reference resistor to GND.
(2) The calibrated R
Table
I/O standards
5–11:
S
and R
R
Stratix V devices support R
calibration is only supported for input configuration of input and bidirectional pins.
Output pin configurations do not support R
R
the I/O standard of the pin where the R
Figure 5–5.
The R
external 100-  or 240-  resistors connected to the RZQ pin and dynamically enables or
disables the transistors until they match. Calibration occurs at the end of device
configuration. When the calibration circuit finds the correct impedance, it powers
down and stops changing the characteristics of the drivers.
T
T
T
OCT final values are pending silicon characterization.
OCT with Calibration
OCT with calibration. When you use R
T
OCT calibration circuit compares the total impedance of the I/O buffer to the
R
T
OCT with Calibration
OCT Setting, R
Uncalibrated R
Transmitter
25
—
—
—
—
—
Output Termination
s
T
()
s
OCT with calibration in all banks. R
Setting, R
Calibrated R
25, 34, 40, 50
34, 40, 48, 60, 80
40, 60, 240
34, 40
34, 40
Z
0
T
25
(2)
OCT is enabled.
s
T
()
(2)
(2)
T
OCT, the V
s
(2)
OCT
OCT with calibration.
V
(2)
REF
(1)
R
20, 30, 40, 60, 120
20, 30, 40, 60, 120
20, 30, 40, 60, 120
Input Termination
Chapter 5: I/O Features in Stratix V Devices
T
V
OCT Setting, R
OCT Support and I/O Termination Schemes
CCIO
CCIO
GND
60, 120
100
100
()
50
(2)
(2)
(2)
(2)
Stratix V OCT
Receiver
of the bank must match
(2)
May 2011 Altera Corporation
T
OCT with
T
Figure 5–5
V
REF
0.6
—
—
—
—
—
(V)
shows
V
1.35
1.25
1.2
1.5
1.2
1.2
(V)
CCIO