DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 399

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
Standard PCS Architecture
Figure 1–21. MSByte and LSByte of the Two-Bit Transmitter Data Straddled Across Two Word Boundaries
Figure 1–22. MSByte and LSByte of the Four-Bit Transmitter Data Straddled Across Two Word Boundaries
May 2011 Altera Corporation
tx_serial_data[15:8]
tx_serial_data[31:16]
tx_serial_data[7:0]
tx_serial_data[15:0]
(MSByte)
(LSByte)
(MSByte)
(LSByte)
Transmitter
D2
D1
D3D4
D1D2
Transmitter
D4
D3
Byte Ordering Block
In single-width mode with the 16- or 20-bit FPGA fabric-transceiver interface, the byte
deserializer receives one data byte (8 or 10 bits) and deserializes it into two data bytes
(16 or 20 bits). Depending on when the receiver PCS logic comes out of reset, the byte
ordering at the output of the byte deserializer may or may not match the original byte
ordering of the transmitted data. The byte misalignment resulting from byte
deserialization is unpredictable because it depends on which byte is being received by
the byte deserializer when it comes out of reset.
Figure 1–21
transmitter data appears straddled across two word boundaries after being byte
deserialized at the receiver.
In double-width modes with a 32-bit FPGA fabric-transceiver interface, the byte
deserializer receives two data bytes (16 bits) and deserializes it into four data bytes
(32 bits).
Figure 1–22
transmitter data appears straddled across two word boundaries after being byte
deserialized at the receiver.
The transceivers have an optional byte ordering block in the receiver datapath that
you can use to restore proper byte ordering before forwarding the data to the FPGA
fabric. The byte ordering block looks for the user-programmed byte ordering pattern
in the byte-deserialized data. You must select a byte ordering pattern that you know
appears at the LSByte(s) position of the parallel transmitter data. If the byte ordering
block finds the programmed byte ordering pattern in the MSByte(s) position of the
byte-deserialized data, it inserts the appropriate number of user-programmed PAD
bytes to push the byte ordering pattern to the LSByte(s) position, thereby restoring
proper byte ordering.
D7D8
D5D6
D6
D5
Serializer
Serializer
Byte
shows a scenario in which the MSByte and LSByte of the two-byte
shows a scenario in which the two MSBytes and LSBytes of the four-byte
Byte
xx D1 D2 D3 D4 D5 D6 xx
xx D1 D2 D3 D4 D5 D6 xx
Deserializer
Deserializer
Byte
Byte
Stratix V Device Handbook Volume 3: Transceivers
D1
xx
D1D2
xx
Receiver
D3
D2
Receiver
D5D6
D3D4
D5
D4
D7D8
xx
D6
xx
rx_serial_data[31:16]
rx_serial_data[15:0]
rx_serial_data[15:8]
rx_serial_data[7:0]
(MSByte)
(LSByte)
(MSByte)
(LSByte)
1–27