DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 251

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Memory Interface Pin Support
Figure 7–3. DQS Pins in Stratix V I/O Banks
May 2011 Altera Corporation
DLL_TL
DLL_BL
DQS1T
DQS62B
8A
3A
1
The DQS and DQSn pins are listed in the Stratix V pin tables as DQSXY and DQSnXY,
respectively, where X indicates the DQ/DQS grouping number and Y indicates
whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the
device. The DQ/DQS pin numbering is based on x4 mode.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS group
the pins belong to and Y indicates whether the group is located on the top (T),
bottom (B), or right (R) side of the device. For example, DQS1T indicates a DQS pin
located on the top side of the device. The DQ pins belonging to that group are shown
as DQ1T in the pin table. For more information, refer to
The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin
table.
The numbering scheme starts from the top-left corner of the device going counter
clockwise in a die-top view.
numbered in a die-top view of the device.
8B
3B
8C
3C
8D
3D
Stratix V Device
8E
4E
Figure 7–3
7E
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
4D
shows how the DQ/DQS groups are
7D
4C
7C
Figure
4B
7B
7–3.
4A
7A
DQS66T
DQS1B
6B
6C
6A
5C
5B
5A
DLL_TR
DLL_BR
7–7
DQS44R
DQS1R