DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 203

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 5: I/O Features in Stratix V Devices
Termination Schemes for I/O Standards
Figure 5–14. HSTL I/O Standard Termination
Note to
(1) This is not applicable for HSUL-12 I/O standard.
May 2011 Altera Corporation
Bi-Directional
OCT Transmit
OCT Receive
Termination
Termination
On-Board
External
OCT in
Pins
Figure
Stratix V
Series OCT 50 Ω
5–14:
OCT 50 Ω
1
Series
Transmitter
Transmitter
Transmitter
Stratix V
Figure 5–14
You cannot use R
“Dynamic OCT” on page
V
GND
CCIO
100 Ω
100 Ω
HSTL Class I
50 Ω
50 Ω
V
50 Ω
shows the details of HSTL I/O termination on Stratix V devices.
50 Ω
REF
V
V
50 Ω
50 Ω
REF
REF
V
V
TT
TT
S
and R
(Note 1)
V
GND
CCIO
V
GND
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
T
Receiver
Receiver
Receiver
Stratix V
5–19.
OCT simultaneously. For more information, refer to
OCT 50 Ω
Series
Parallel OCT
Stratix V
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Stratix V
Series OCT 25 Ω
OCT 25 Ω
Series
Transmitter
Transmitter
Transmitter
Stratix V
V
GND
CCIO
100 Ω
100 Ω
V
V
TT
V
TT
TT
50 Ω
50 Ω
50 Ω
HSTL Class II
50 Ω
50 Ω
50 Ω
50 Ω
V
REF
V
V
REF
REF
50 Ω
50 Ω
V
V
TT
TT
V
GND
CCIO
V
GND
CCIO
100 Ω
100 Ω
100 Ω
100 Ω
Receiver
Receiver
Receiver
Stratix V
OCT 25 Ω
Series
Parallel OCT
Stratix V
5–27