DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 196

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–20
OCT Calibration
Figure 5–8. OCT Calibration Block and RZQ Pin Location—Preliminary
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
LVDS Input R
Stratix V devices support OCT for differential LVDS input buffers with a nominal
resistance value of 100  , as shown in
banks. You can use R
Figure 5–7. Differential Input OCT
Stratix V devices support calibrated R
exceptions for dedicated configuration pins. You can calibrate using any of the
available four to eight OCT calibration blocks, depending on the density of the device.
Each calibration block contains one RZQ pin.
Figure 5–8
RZQ pin
RZQ pin
Bank 3A
Bank 8A
D
OCT
Bank 8B
Bank 3B
shows the location of I/O banks with OCT calibration blocks and RZQ pins.
Bank 3C
Bank 8C
Transmitter
This is a top view of the silicon die that corresponds to a reverse view for
flip chip packages. This figure illustrates the highest density for Stratix V devices.
More information about other Stratix V devices bank locations will be
available in future releases of the Stratix V device pin-out files.
D
Bank 3D
Bank 8D
OCT when both the V
Bank 8E
Bank 3E
Bank 7E
Bank 4E
S
Figure
and calibrated R
Bank 7D
Bank 4D
Z
Z
0
0
= 50 Ω
= 50 Ω
CCIO
5–7. R
Bank 7C
Bank 4C
I/O bank with OCT calibration
block and RZQ pin
and V
D
Bank 7B
Bank 4B
Chapter 5: I/O Features in Stratix V Devices
OCT is supported in all I/O
T
CCPD
on all I/O pins with
Bank 7A
Bank 4A
100 Ω
RZQ pin
RZQ pin
Receiver
is set to 2.5 V.
May 2011 Altera Corporation
OCT Calibration