DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 508

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–6
Figure 5–5. 10G PCS Low Latency Datapath with the Gear Box Ratio of 32:64
Stratix V Device Handbook Volume 3: Transceivers
rx_coreclk
tx_coreclk
tx_clkout
rx_clkout
Fabric
FPGA
/2
/2
64
64
CMU PLL
Figure 5–5
interface width (64 bits) is exactly twice the internal transceiver datapath width. You
can divide the tx_clkout and rx_clkout in the FPGA fabric by two, and use them to
clock the write side of TX FIFO and the read side of RX FIFO, respectively. Select the
tx_coreclk and the rx_coreclk ports in the Low Latency PHY IP core and connect
the divided clock to these ports, as shown in
Figure 5–6
an integral multiple of the FPGA fabric interface width. You must use a fractional PLL
to provide the appropriate clock frequency to the write side of the TX FIFO. Set the
division factor in the fractional PLL so that its output frequency is equal to the
transmitter data rate divided by 66 or 50. The clock source that provides the input
reference clock to the fractional PLL and the CMU PLL must be the same because the
TX FIFO operates as a phase compensation FIFO; therefore, the clock requires a 0
PPM between the read and write sides.
(From the ×1 Clock Lines)
Serial Clock
shows the configuration where the gear box ratio is 32:64. The FPGA fabric
shows the clocking scheme when the gear box ratio (40:66 or 40:50) is not
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Clock Divider
Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Parallel and Serial Clocks
(Only from the Central Clock Divider)
Figure
5–5.
Transmitter 10G PCS
Receiver 10G PCS
32
10G Low Latency Configuration
May 2011 Altera Corporation
32
Transmitter PMA
Receiver PMA
Parallel Clock
Serial Clock
Parallel Clock and Serial Clock
Input Reference
Clock