DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 161

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Stratix V PLLs
Figure 4–17. PLL Locations for 5SGXA5 and 5SGXA7 Devices
Note to
(1) Every index represents one fractional PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the
May 2011 Altera Corporation
Quartus II software Chip Planner.
Figure
4–17:
COR_X0_Y122
COR_X0_Y113
LR_X0_Y100
LR_X0_Y91
LR_X0_Y75
LR_X0_Y66
LR_X0_Y53
LR_X0_Y44
LR_X0_Y29
LR_X0_Y20
COR_X0_Y10
COR_X0_Y1
Figure 4–17
4
4
4
4
4
4
shows the PLL locations for 5SGXA5 and 5SGXA7 devices.
CLK[20..23][p,n]
CLK[0..3][p,n]
4 Logical clocks
4
Pins
Logical clocks
Pins
CLK[16..19][p,n]
CEN_X98_Y118
CEN_X98_Y109
CEN_X98_Y11
CEN_X98_Y2
CLK[4..7][p,n]
5SGXA5
5SGXA7
4 Logical clocks
4 Logical clocks
Pins
Pins
(Note 1)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CLK[12..15][p,n]
CLK[8..11][p,n]
4 Logical clocks
4 Logical clocks
Pins
Pins
4
4
4
4
4
4
COR_X210_Y122
COR_X210_Y113
COR_X210_Y10
COR_X210_Y1
LR_X210_Y100
LR_X210_Y91
LR_X210_Y75
LR_X210_Y66
LR_X210_Y53
LR_X210_Y44
LR_X210_Y29
LR_X210_Y20
4–21