DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 470

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–14
Figure 4–10. Channel Placement Guidelines in Interlaken Configurations
Stratix V Device Handbook Volume 3: Transceivers
When you use a CMU PLL:
Within a Transceiver Bank
f
1
Interlaken Lane 5
Interlaken Lane 4
Interlaken Lane 3
Interlaken Lane 2
Interlaken Lane 0
Interlaken Lane 5
Interlaken Lane 3
Interlaken Lane 2
Interlaken Lane 1
Interlaken Lane 0
CMU PLL
CMU PLL
Transceiver Channel Placement Guidelines
Stratix V devices allow placing up to five Interlaken channels in a transceiver bank.
Figure 4–10
using the CMU PLL or when using the ATX PLL.
To enable the ATX PLL, you must select a minimum bond size of six in the Bonded
Group Size parameter in the Interlaken PHY IP. You must also select the ATX PLL
from the Quartus II Assignment Editor.
For more information about channel placement guidelines, refer to the
Clocking
section in the Transceiver Clocking in Stratix V Devices chapter.
Ch 3
Ch 3
Ch 4
Ch 4
Ch 5
Ch 5
shows the legal Interlaken channel locations in a transceiver bank when
×1 Clock Line
×1 Clock Line
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
When you use an ATX PLL:
Within a Transceiver Bank
Interlaken Ch 4
Interlaken Ch 3
Interlaken Ch 2
Interlaken Ch 1
Interlaken Ch 0
Interlaken Ch 4
Interlaken Ch 3
Interlaken Ch 2
Interlaken Ch 1
Interlaken Ch 0
Interlaken Ch 5
Interlaken Ch 5
May 2011 Altera Corporation
Internal
Interlaken