DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 388

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–16
Stratix V Device Handbook Volume 3: Transceivers
c
Programmable Output Differential Voltage
You can customize the differential output voltage to handle different trace lengths,
various backplanes, and receiver requirements.
and differential waveforms.
Figure 1–15. V
Programmable Pre-Emphasis
The programmable pre-emphasis module in each transmit buffer boosts high
frequencies in the transmit data signal, which might be attenuated in the transmission
media. Using pre-emphasis can maximize the data eye opening at the far-end receiver.
The transceivers provide three pre-emphasis taps—pre-tap, first post-tap, and second
post-tap. The pre-tap sets the pre-emphasis on the data bit before the transition. The
first post-tap and second post-tap set the pre-emphasis on the transition bit and the
successive bit, respectively. The pre-tap and second post-tap also provide inversion
control, shown by negative values.
Serializer
The serializer converts the incoming low-speed parallel data from the transceiver PCS
to high-speed serial data and sends it to the transmitter buffer. The serializer supports
an 8- and 10-bit, 16- and 20-bit, and 32- and 40-bit serialization factor. The serializer
block sends out the LSB of the input data first. The transmitter serializer also has
polarity inversion and bit reversal capabilities.
Transmitter Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be
swapped during board layout. Solutions such as a board re-spin or major updates to
the logic in the FPGA fabric can be expensive. The transmitter polarity inversion
feature is provided to correct this situation.
A high value on the tx_invpolarity port inverts the polarity of every bit of the input
data word to the serializer in the transmitter datapath. Because inverting the polarity
of each bit has the same effect as swapping the positive and negative signals of the
differential link, correct data is sent to the receiver. The dynamic signal
tx_invpolarity might cause initial disparity errors at the receiver of an 8B/10B
encoded link. The downstream system must be able to tolerate these disparity errors.
If the polarity inversion is asserted midway through a serializer word, the word will
be corrupted.
V
OD
(Differential)
Single-Ended Waveform
OD
Differential Waveform
=V
A
(Differential) Signal Level
– V
B
+V
OD
Chapter 1: Transceiver Architecture in Stratix V Devices
V
±V
OD
OD
(Differential)
Figure 1–15
shows the single-ended
–V
May 2011 Altera Corporation
OD
V
V
+700
0 V Differential
–700
A
B
PMA Architecture