DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 472

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–16
Figure 4–11. Stratix V Transceivers in a PIPE Configuration
Note to
(1) Applies to a PCS-hard IP interface. A PCS-FPGA fabric interface frequency is limited to 250 MHz.
Stratix V Device Handbook Volume 3: Transceivers
Figure
Transceiver Datapath Configuration
Transceiver PHY IP
Bonded Data Rate
Reference Clock
Number of Bonded Channels
PMA-PCS Interface Width
8B/10B Encoder/Decoder
Rate Match FIFO
PCIe hard IP
Byte SERDES
PCS-hard IP or
PCS-FPGA Fabric Interface Width
PCS-hard IP or
PCS-FPGA Fabric Interface Frequency
Word Aligner (Pattern)
4–11:
Figure 4–11
Transceiver datapath clocking varies between non-bonded (×1) and bonded (×4 and
×8) configurations.
For more information about transceiver datapath clocking in different PIPE
configurations, refer to
shows the transceiver configurations allowed in a PIPE configuration.
“Transceiver Clocking” on page
Disabled
250 MHz
Enabled
8-Bit
2.5 Gpbs for Gen1
Synchronization
(/K28.5/K28.5-/)
State Machine
100/125 MHz
Automatic
x1, x4, x8
Enabled
Enabled
10-Bit
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
250 MHz
Disabled
8-Bit
Disabled
125 MHz
Enabled
16-Bit
PIPE
4–24.
5.0 Gbps for Gen2
500 MHz (1)
Synchronization
(/K28.5/K28.5-/)
Disabled
Enabled
State Machine
PCI Express (PCIe)—Gen1 and Gen2
100/125 MHz
x1, x4, x8
8-Bit
Automatic
Enabled
Enabled
10-Bit
May 2011 Altera Corporation
Disabled
250 MHz
Enabled
16-Bit