DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 49

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
May 2011 Altera Corporation
Periphery Performance
1
JTAG Configuration Specifications
Table 2–24
Table 2–24. JTAG Timing Parameters and Values for Stratix V Devices—Preliminary
Temperature Sensing Diode Specifications
Table 2–25
Table 2–25. External Temperature Sensing Diode Specifications for Stratix V Devices—
Preliminary
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of typical 167 MHz and 1.2 LVCMOS at 100 MHz interfacing frequency with
10 pF load.
Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
t
t
t
t
t
t
t
t
t
Notes to
(1) These numbers are preliminary pending silicon characterization.
(2) A 1 ns adder is required for each V
I
V
Series resistance
Diode ideality factor
JCP
JCH
JCL
JPSU (TDI)
JPSU (TMS)
JPH
JPCO
JPZX
JPXZ
bias
bias,
Symbol
, diode source current
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
voltage across diode
Table
lists the JTAG timing parameters and values for Stratix V devices.
lists the specifications for the Stratix V temperature sensing diode.
2–24:
Description
TCK clock period
TCK clock high time
TCK clock low time
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
CCIO
Description
voltage step down from 3.0 V. For example, t
Stratix V Device Handbook Volume 1: Overview and Datasheet
Min
0.3
—
—
8
Typ
—
—
—
—
Min
30
14
14
—
—
—
2
3
5
JPCO
= 12 ns if V
11
14
14
1.030
Max
200
Max
0.9
< 5
—
—
—
—
—
—
(2)
(2)
(2)
CCIO
(Note 1)
of the TDO
Unit
Unit
A
—
ns
ns
ns
ns
ns
ns
ns
ns
ns

V
2–21