DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 427

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Transceiver Clocking in Stratix V Devices
Internal Clocking
Figure 2–9. Transmitter Standard PCS Clocking
Notes to
(1) Only available in the central clock dividers of channel 1 and channel 4 in a transceiver bank.
(2) ×1 clock lines can be driven either by a CMU PLL or ATX PLL.
May 2011 Altera Corporation
tx_coreclkin
Fabric
CMU PLL
FPGA
tx_clkout
Figure
(From the ×1 Clock Lines)
Serial Clock
2–9:
f
Figure 2–9
As shown in
clock to the serializer of the transmitter PMA and the parallel clock to the transmitter
PCS and the serializer of the transmitter PMA.
In the 10G PCS channel, the parallel clock is used by all the blocks up to the read side
of the transmitter (TX) FIFO. This clock is also forwarded to the FPGA fabric to
interface the FPGA fabric with the transceiver.
In the standard PCS channel, the parallel clock is used by all the blocks up to the read
side of the TX phase compensation FIFO in all configurations that do not use the byte
serializer block. For configurations that use the byte serializer block, the clock is
divided by a factor of 2 for the byte serializer and the read side of the TX phase
compensation FIFO. The clock used to clock the read side of the TX phase
compensation FIFO is also forwarded to the FPGA fabric to interface the FPGA fabric
with the transceiver.
For more information about clocking schemes used in different configurations, refer
to the
Configurations in Stratix V Devices
(2)
Transceiver Protocol Configurations in Stratix V Devices
Central/ Local Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
shows clocking for the transmitter standard PCS and transmitter PMA.
Figure 2–8
/2
and
Clock Divider
Figure
chapters.
2–9, the clock divider block provides the serial
Parallel and Serial Clocks
(To the ×6 clock lines) (1)
Stratix V Device Handbook Volume 3: Transceivers
Transmitter Standard PCS
and
Transceiver Custom
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Transmitter PMA
2–11