DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 206

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–30
Figure 5–16. Differential HSTL I/O Standard Termination
Note to
(1) This is not applicable for
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Termination
Termination
On-Board
External
OCT
Figure
Stratix V
Series OCT 25 Ω
Stratix V
Series OCT 50 Ω
5–16:
Transmitter
Transmitter
differential HSUL-12
Differential HSTL Class I
Z
Z
0
0
= 50 Ω
= 50 Ω
50 Ω
50 Ω
50 Ω
V
GND
CCIO
I/O standard.
V
100 Ω
100 Ω
TT
V
TT
50 Ω
V
GND
CCIO
Receiver
100 Ω
100 Ω
Receiver
(Note 1)
Stratix V
Series OCT 25 Ω
Transmitter
Transmitter
50 Ω
V
V
TT
TT
50 Ω
50 Ω
Chapter 5: I/O Features in Stratix V Devices
V
TT
Z
Z
V
0
0
TT
= 50 Ω
= 50 Ω
Termination Schemes for I/O Standards
50 Ω
Differential HSTL Class II
50 Ω
50 Ω
V
50 Ω
GND
CCIO
May 2011 Altera Corporation
100 Ω
100 Ω
V
TT
V
TT
V
GND
50 Ω
CCIO
Receiver
100 Ω
100 Ω
Receiver