DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 278

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

8–4
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
f
1
■
■
■
For more information about the MSEL pin settings, refer to the
Security, and Remote System Upgrades in Stratix V Devices
Figure 8–2
Figure 8–2. Relationship between t
The Stratix V POR implements a modularized design structure to monitor the
supplies gating the main POR. Each external power supply being monitored has a
base POR, which employs a generic design to detect the corresponding voltage level
for proper functionality.
It also checks for functionality of I/O level shifters powered by the V
V
individual PORs to release the POR signal so that the control block can start
programming the device. The Stratix V main POR also employs a modularized
structure to enable brown-out detection on a power supply and also to possibly
expand the number of power supplies being monitored.
All configuration-related dedicated and dual function I/O pins must be powered by
the V
CCPGM
For the standard POR delay mode, the POR delay time is 100 to 300 ms.
For the fast POR delay mode, the POR delay time is 4 to 12 ms.
The POR maximum pulse width is 12 ms, which leaves enough time after the POR
trip for the PCI Express
CCPGM
first power supply
power supplies during power-up mode. The main POR waits for all the
shows the relationship between t
power supply.
Volts
®
(PCIe
last power supply
t
RAMP
RAMP
®
) to initialize.
Chapter 8: Hot Socketing and Power-On Reset in Stratix V Devices
and POR Delay
RAMP
and POR delay.
POR delay
chapter.
Configuration, Design
configuration time
May 2011 Altera Corporation
Power-On Reset Circuitry
CCPD
time
and